Instruction pre-fetch amount control with reading amount register flag set based on pre-detection of conditional branch-select instruction

Abstract

An architecture of method for fetching microprocessor's instructions is provided to pre-fetch and pre-decode a next instruction. If the instruction pre-decoded is found a conditional branch instruction, an instruction reading-amount register is set for reading two instructions next to the current instruction in the program memory, or one is read instead if the next instruction is found an instruction other than the conditional branch one so as to waive reading of unnecessary program memory and thereby reduce power consumption.