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超大型積體電路之測試與可測試設計

dc.contributor.author李崇仁en_US
dc.contributor.department交通大學電子工程系zh_TW
dc.date.accessioned2014-12-13T10:36:52Z
dc.date.available2014-12-13T10:36:52Z
dc.date.issued1999en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.identifier.govdocNSC88-2215-E009-062zh_TW
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=418219&docId=74193en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/94228
dc.language.isozh_TWen_US
dc.subject超大型積體電路zh_TW
dc.subject可測試性設計zh_TW
dc.subject靜態電流測試zh_TW
dc.subject振盪環測試zh_TW
dc.subject錯誤診斷zh_TW
dc.subjectVLSIen_US
dc.subjectIDDQ testingen_US
dc.subjectBurn-in testingen_US
dc.subjectOscillation ring testingen_US
dc.subjectFault diagnosisen_US
dc.title超大型積體電路之測試與可測試設計zh_TW
dc.titleVLSI Testing and Design for Testabilityen_US
dc.typePlanen_US

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