The State-of-the-Art Mobility Enhancing Schemes for High-Performance Logic CMOS Technologies

Abstract

In this talk, an overview of the mobility enhancing techniques for high performance/low power CMOS technologies will be introduced first. Three categories of mobility enhancing schemes with global strain, local strain, and hybrid-substrate engineering, will be discussed next. Either nMOSET or pMOSFET has their respective strategies for achieving the best device performance. However, the strain technique has indeed raised reliability issues. Different reliability issues have been observed for different strain technologies. In the past several years, we have paid much more attention on the current performance of these technologies, the device reliability study has not been sufficient in the previous studies. As a consequence, this talk will also address the importance of these mobility enhancing schemes and their impact on the device reliability for advanced CMOS technologies which utilize strain schemes for current enhancement.