POSA: Power-State-Aware Buffered Tree Construction

dc.citation.epage	787	en_US
dc.citation.spage	787	en_US
dc.contributor.author	Jiang, Iris Hui-Ru	en_US
dc.contributor.author	Wu, Ming-Hua	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:23:44Z
dc.date.available	2014-12-08T15:23:44Z
dc.date.issued	2009	en_US
dc.description.abstract	Buffering without considering power states in multiple supply voltage designs may result in infeasible signals. POSA is the first work to handle this issue. Our buffered tree guarantees feasibility all the times, even when some parts of the design shut down. This feature is one of the key techniques to fulfill power-aware design methodology.	en_US
dc.identifier.isbn	978-1-4244-3827-3	en_US
dc.identifier.journal	ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/16555
dc.identifier.wosnumber	WOS:000275929800201
dc.language.iso	en_US	en_US
dc.title	POSA: Power-State-Aware Buffered Tree Construction	en_US
dc.type	Proceedings Paper	en_US

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