A 1-100Mb/s 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Network

dc.citation.epage	232	en_US
dc.citation.spage	229	en_US
dc.citation.woscount	0	en_US
dc.contributor.author	Chen, Chih-Lung	en_US
dc.contributor.author	Wu, Sheng-Jhan	en_US
dc.contributor.author	Chang, Hsie-Chia	en_US
dc.contributor.author	Lee, Chen-Yi	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2017-04-21T06:49:42Z
dc.date.available	2017-04-21T06:49:42Z
dc.date.issued	2014	en_US
dc.description.abstract	A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1 similar to 100Mb/s with power consumption of 0.5 similar to 9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.	en_US
dc.identifier.isbn	978-1-4799-4089-9	en_US
dc.identifier.journal	2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/135869
dc.identifier.wosnumber	WOS:000380484900058	en_US
dc.language.iso	en_US	en_US
dc.title	A 1-100Mb/s 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Network	en_US
dc.type	Proceedings Paper	en_US

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