高遷移率鍺與三五族通道磊晶於矽基板上與其應用於次22nm場效電晶體之製作
Abstract
到今日為止，邏輯元件尺寸微縮化仍是製程技術努力的方向；然而矽金氧半場效電晶體已遭遇到物理極限，製程技術或達到良好元件性能的困難度已隨之上升。單純地縮減通道長度或將介電層厚度持續降低已無法得到良好的電流開關比、高電流驅動力、低漏電和極佳的可靠度的需求。
本研究計畫將整合三五族及鍺製作先進元件結構於低成本矽基板上：(1)磊晶鍺或砷化銦鎵於絕緣上矽基板並製作環繞閘極式奈米線電晶體及(2)平面式及非平面式多閘極磊晶砷化銦鎵量子井載子通道之高速場效電晶體及(3) 磊晶砷化銦鎵載子通道及鍺源極之穿隧式場效電晶體於矽基板。使用這些磊晶材料當作載子通道將可同時提供較低的等效電子及電洞質量，相較以傳統矽為通道的元件，大大提升驅動電流。而在15奈米以下的技術結點，環繞閘極式奈米線電晶體、量子井場效電晶體以及穿隧式場效電晶體被視為可能取代傳統金氧半場效電晶體元件結構。再整合於矽基板上，將可實現高性能、低成本之互補式金氧半電晶體前瞻性技術，我們將有系統地建立元件製程技術並深入探討這些新穎元件結構的電特性及可靠度的分析。
Nowadays, the CMOS technologies still continuously aim at scaling device’s dimension as small as possible. Nevertheless, the feature size of conventional Si MOS-FET has encoun-tered its fundamental physical limits; the accompanying difficulties in either process technol-ogy or achieving device performance are also increased. Simply shrinking the channel length and/or the dielectric thickness already can’t realize the excellent switching ratio, high driving capability, low leakage current, and acceptable reliability, respectively. In this project, we will integrate III-V and/or Ge to fabricate novel device structures on low-cost traditional Si substrates: (i) Epitaxy of Ge or InxGa1-xAs on SOI substrates and fa-bricating gate-all-around (GAA) nanowire MOSFETs (ii) Fabrication of planer and non-planer multi-gate InxGa1-xAs epitaxy quantum-well MOSFETs and (iii) Epitaxy of Inx-Ga1-xAs channel and Ge source on Si substrate and fabricating tunneling FETs . These epitax-ial materials being as a transport channel, where possess a lower hole and electron effective mass, are expected to provide a higher driving current as compared to traditionally Si-based channel transistors. For the 15nm technology nodes and beyond, gate-all-around nanowire MOSFET, quantum-well FET, and tunneling FET are considered potential candidates to re-place conventional Si MOSFETs. And to integrate with Si substrates, the high performance and low-cost CMOS transistors can be realized. We will systematically develop the process technologies and analyze the electrical characteristics and reliability of these novel strictures in depth.
Nowadays, the CMOS technologies still continuously aim at scaling device’s dimension as small as possible. Nevertheless, the feature size of conventional Si MOS-FET has encoun-tered its fundamental physical limits; the accompanying difficulties in either process technol-ogy or achieving device performance are also increased. Simply shrinking the channel length and/or the dielectric thickness already can’t realize the excellent switching ratio, high driving capability, low leakage current, and acceptable reliability, respectively. In this project, we will integrate III-V and/or Ge to fabricate novel device structures on low-cost traditional Si substrates: (i) Epitaxy of Ge or InxGa1-xAs on SOI substrates and fa-bricating gate-all-around (GAA) nanowire MOSFETs (ii) Fabrication of planer and non-planer multi-gate InxGa1-xAs epitaxy quantum-well MOSFETs and (iii) Epitaxy of Inx-Ga1-xAs channel and Ge source on Si substrate and fabricating tunneling FETs . These epitax-ial materials being as a transport channel, where possess a lower hole and electron effective mass, are expected to provide a higher driving current as compared to traditionally Si-based channel transistors. For the 15nm technology nodes and beyond, gate-all-around nanowire MOSFET, quantum-well FET, and tunneling FET are considered potential candidates to re-place conventional Si MOSFETs. And to integrate with Si substrates, the high performance and low-cost CMOS transistors can be realized. We will systematically develop the process technologies and analyze the electrical characteristics and reliability of these novel strictures in depth.