A High-Speed HBT Prescaler Based on the Divide-by-Two Topology
| dc.citation.epage | 758 | en_US |
| dc.citation.spage | 755 | en_US |
| dc.contributor.author | Wei, Hung-Ju | en_US |
| dc.contributor.author | Meng, Chinchun | en_US |
| dc.contributor.author | Chang, Yuwen | en_US |
| dc.contributor.author | Lin, Yi-Chen | en_US |
| dc.contributor.author | Huang, Guo-Wei | en_US |
| dc.contributor.department | 電信工程研究所 | zh_TW |
| dc.contributor.department | Institute of Communications Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:13:45Z | |
| dc.date.available | 2014-12-08T15:13:45Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | This paper demonstrates the Divide-by4/5 prescalers with merged AND gates in 2 mu m GaInP/GaAs heterojunction bipolar transistor (HBT) and 035 mu m SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (f(tau)), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GaInP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz similar to 8 GHz at the cost of power consumption. | en_US |
| dc.identifier.isbn | 978-1-4244-0748-4 | en_US |
| dc.identifier.journal | 2007 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/10633 | |
| dc.identifier.wosnumber | WOS:000261353300193 | |
| dc.language.iso | en_US | en_US |
| dc.subject | GaInP/GaAs HBT | en_US |
| dc.subject | SiGe HBT | en_US |
| dc.subject | Dual-Modulus | en_US |
| dc.subject | Divide-by4/5 | en_US |
| dc.subject | Prescaler | en_US |
| dc.subject | Emitter Couple Logic (ECL) | en_US |
| dc.title | A High-Speed HBT Prescaler Based on the Divide-by-Two Topology | en_US |
| dc.type | Proceedings Paper | en_US |
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