A 2.5 Gbps CMOS fully integrated optical receicer with lateral PIN detector

dc.citation.epage	296	en_US
dc.citation.spage	293	en_US
dc.contributor.author	Chen, Wei-Zen	en_US
dc.contributor.author	Huang, Shih-Hao	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:08:28Z
dc.date.available	2014-12-08T15:08:28Z
dc.date.issued	2007	en_US
dc.description.abstract	This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mV(pp) to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mu m CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm(2).	en_US
dc.identifier.isbn	978-1-4244-0786-6	en_US
dc.identifier.journal	PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/6534
dc.identifier.wosnumber	WOS:000252233200067
dc.language.iso	en_US	en_US
dc.title	A 2.5 Gbps CMOS fully integrated optical receicer with lateral PIN detector	en_US
dc.type	Article	en_US

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