A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation

Abstract

A Poly-Si TFT model for circuit simulation in Spice is presented, combined with a device degradation model for the first time to evaluate the circuit reliability. Both I-V and C-V models for the whole device operating regime have been developed. In the I-V model, emphasis has been taken to derive the mobility degradation induced by the grain boundary potantial barrier height and trap density. The small geometry effect, off-state current and the parasitic BJT effect are also considered in the model. Good agreements between modeled and experimental data were achieved. To evaluate the circuit reliability after electrical stress, the device reliability model has also been developed. Finally, simulation a 27-stage ring oscillator has been demonstrated, which shows delay time of about 1 nsec per stage.