Test structure on SCR device in waffle layout for RE ESD protection
| dc.citation.epage | 199 | en_US |
| dc.citation.spage | 196 | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.author | Lin, Chun-Yu | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:09:20Z | |
| dc.date.available | 2014-12-08T15:09:20Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | With the highest ESD level in a smallest layout area, SCR device was used as effective on-chip ESD protection device in CMOS technology. In this paper, a waffle layout test structure of SCR is proposed to investigate the current spreading efficiency for ESD protection. The SCR in waffle layout structure has smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to on-chip ESD protection device can be reduced. The proposed waffle SCR is suitable for on-chip ESD protection in RF applications. | en_US |
| dc.identifier.doi | 10.1109/ICMTS.2007.374482 | en_US |
| dc.identifier.isbn | 978-1-4244-0780-4 | en_US |
| dc.identifier.issn | 1071-9032 | en_US |
| dc.identifier.journal | 2007 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ICMTS.2007.374482 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/7124 | |
| dc.identifier.wosnumber | WOS:000247663800038 | |
| dc.language.iso | en_US | en_US |
| dc.title | Test structure on SCR device in waffle layout for RE ESD protection | en_US |
| dc.type | Article | en_US |