多工作線處理器架構與編譯器設計
| dc.contributor.author | 曾建超 | en_US |
| dc.contributor.author | TSENG CHIEN-CHAO | en_US |
| dc.contributor.department | 國立交通大學資訊工程研究所 | zh_TW |
| dc.date.accessioned | 2014-12-13T10:39:22Z | |
| dc.date.available | 2014-12-13T10:39:22Z | |
| dc.date.issued | 1995 | en_US |
| dc.description.sponsorship | 行政院國家科學委員會 | zh_TW |
| dc.identifier.govdoc | NSC84-2213-E009-082 | zh_TW |
| dc.identifier.uri | https://www.grb.gov.tw/search/planDetail?id=169305&docId=28390 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/96410 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | 多工作線處理器架構與編譯器設計 | zh_TW |
| dc.title | Multithreaded Processor Architectrue and Compiler Design | en_US |
| dc.type | Plan | en_US |
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