Characterizing bit permutation networks

Abstract

In recent years, many multistage interconnection networks using 2 x 2 switching elements have been proposed for parallel architectures. Typical examples are baseline networks, banyan networks, shuffle-exchange networks and their inverses. As these networks are blocking, such networks with extra stages have also been studied extensively. These include Benes networks and Delta + Delta' networks. Recently, Hwang, Liaw and Yeh studied k-extra-stage networks which is a generalization of the above networks. They also investigated the equivalence issue among some of these networks. In this paper, we study a more general class of networks, which we call (m + 1)-stage d-nary bit permutation networks. We characterize the equivalence of such networks by sequence of positive integers.