A FUZZY-NEURO APPROACH FOR TIMING-DRIVEN SYSTEM PARTITIONING IN VLSI MULTI-CHIP DESIGN
| dc.citation.epage | 307 | en_US |
| dc.citation.spage | 302 | en_US |
| dc.contributor.author | CHANG, RI | en_US |
| dc.contributor.author | HSIAO, PY | en_US |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| dc.contributor.department | Department of Computer Science | en_US |
| dc.date.accessioned | 2014-12-08T15:27:53Z | |
| dc.date.available | 2014-12-08T15:27:53Z | |
| dc.date.issued | 1994 | en_US |
| dc.identifier.isbn | 0-7803-1897-8 | en_US |
| dc.identifier.journal | PROCEEDINGS OF THE THIRD IEEE CONFERENCE ON FUZZY SYSTEMS - IEEE WORLD CONGRESS ON COMPUTATIONAL INTELLIGENCE, VOLS I-III | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/20138 | |
| dc.identifier.wosnumber | WOS:A1994BC17S00054 | |
| dc.language.iso | en_US | en_US |
| dc.title | A FUZZY-NEURO APPROACH FOR TIMING-DRIVEN SYSTEM PARTITIONING IN VLSI MULTI-CHIP DESIGN | en_US |
| dc.type | Proceedings Paper | en_US |
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