ON-CHIP INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20110042782 | zh_TW |
| dc.contributor.author | CHAO, TZU-YUAN | en_US |
| dc.contributor.author | HSU, MING-CHIEH | en_US |
| dc.contributor.author | CHENG, YU-TING | en_US |
| dc.contributor.author | CHEN, CHIH | en_US |
| dc.contributor.author | LIU, CHIEN-MIN | en_US |
| dc.date.accessioned | 2014-12-16T06:15:27Z | |
| dc.date.available | 2014-12-16T06:15:27Z | |
| dc.date.issued | 2011-02-24 | en_US |
| dc.description.abstract | The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered. | zh_TW |
| dc.identifier.govdoc | H01L029/86 | zh_TW |
| dc.identifier.govdoc | H01L021/02 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/105335 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | ON-CHIP INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | zh_TW |
| dc.type | Patents | en_US |