5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner
| dc.citation.epage | 304 | en_US |
| dc.citation.spage | 301 | en_US |
| dc.citation.woscount | 1 | en_US |
| dc.contributor.author | Hsiao, Yu-Chih | en_US |
| dc.contributor.author | Meng, Chinchun | en_US |
| dc.contributor.author | Syu, Jin-Siang | en_US |
| dc.contributor.author | Lin, Chung-Yo | en_US |
| dc.contributor.author | Wong, Shyh-Chyi | en_US |
| dc.contributor.author | Huang, Guo-Wei | en_US |
| dc.contributor.department | 電機工程學系 | zh_TW |
| dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2019-04-02T06:04:37Z | |
| dc.date.available | 2019-04-02T06:04:37Z | |
| dc.date.issued | 2012-01-01 | en_US |
| dc.description.abstract | This paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply. | en_US |
| dc.identifier.journal | 2012 7TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/150603 | |
| dc.identifier.wosnumber | WOS:000318630900076 | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | low power | en_US |
| dc.subject | direct-conversion receiver | en_US |
| dc.subject | vertical-NPN bipolar junction transistor | en_US |
| dc.title | 5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner | en_US |
| dc.type | Proceedings Paper | en_US |
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