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Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs

dc.citation.woscount0en_US
dc.contributor.authorLee, Ho-Peien_US
dc.contributor.authorTseng, Kuei-Yangen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2019-04-02T06:04:21Z
dc.date.available2019-04-02T06:04:21Z
dc.date.issued2018-01-01en_US
dc.identifier.issn1930-8868en_US
dc.identifier.journal2018 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/150744
dc.identifier.wosnumberWOS:000444900700025en_US
dc.language.isoen_USen_US
dc.titleInterface Discrete Trap Induced Variability for Negative Capacitance FinFETsen_US
dc.typeProceedings Paperen_US

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