On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process

dc.citation.epage	+	en_US
dc.citation.spage	2281	en_US
dc.citation.woscount	7	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Chiu, Po-Yen	en_US
dc.contributor.author	Tsai, Fu-Yi	en_US
dc.contributor.author	Chang, Yeong-Jar	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2017-04-21T06:49:33Z
dc.date.available	2017-04-21T06:49:33Z
dc.date.issued	2009	en_US
dc.description.abstract	A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 degrees C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.	en_US
dc.identifier.isbn	978-1-4244-3827-3	en_US
dc.identifier.journal	ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/134992
dc.identifier.wosnumber	WOS:000275929801257	en_US
dc.language.iso	en_US	en_US
dc.title	On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process	en_US
dc.type	Proceedings Paper	en_US

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