Electrical test structure applying 3D-ICS bonding technology for stacking error measurement
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 08546952 | zh_TW |
| dc.contributor.author | Chen Kuan-Neng | en_US |
| dc.contributor.author | Li Shih-Wei | en_US |
| dc.date.accessioned | 2014-12-16T06:13:58Z | |
| dc.date.available | 2014-12-16T06:13:58Z | |
| dc.date.issued | 2013-10-01 | en_US |
| dc.description.abstract | A 3D integrated circuit including a first wafer and a second wafer is provided. The first wafer includes a first conduction pattern. The second wafer includes a second conduction pattern which is electrically connected to the first conduction pattern. A displacement between the first wafer and the second wafer is determined by a resistance of the first conduction pattern and the second conduction pattern. | zh_TW |
| dc.identifier.govdoc | H01L023/48 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/104437 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | Electrical test structure applying 3D-ICS bonding technology for stacking error measurement | zh_TW |
| dc.type | Patents | en_US |