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InAs-Channel Metal-Oxide-Semiconductor HEMTs with Atomic-Layer-Deposited Al2O3 Gate Dielectric

dc.citation.epage92en_US
dc.citation.spage87en_US
dc.citation.volume25en_US
dc.citation.woscount0en_US
dc.contributor.authorChang, Chia-Yuanen_US
dc.contributor.authorChang, Edward Yien_US
dc.contributor.authorHuang, Wei-Chingen_US
dc.contributor.authorSu, Yung-Hsuanen_US
dc.contributor.authorTrinh, Hai-Dangen_US
dc.contributor.authorHsu, Heng-Tungen_US
dc.contributor.authorMiyamoto, Yasuyukien_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.date.accessioned2019-04-02T06:04:22Z
dc.date.available2019-04-02T06:04:22Z
dc.date.issued2009-01-01en_US
dc.description.abstractThe performance of n-type metal-oxide-semiconductor HEMTs with an InAs-channel using atomic-layer-deposited Al2O3 as gate dielectric has been fabricated and evaluated. The device performances of a set of scaled transistors with different gate dielectric thicknesses of 3, 5 and 7 nm have been investigated to determine whether the architecture of Al2O3 dielectric on InAs-channel HEMT can demonstrate good properties at low bias conditions for high-speed, high performance CMOS applications. The results indicate that the high-performance InAs-channel MOS-HEMTs with an ALD Al2O3 gate dielectric are promising candidates for advanced post-Si CMOS applications.en_US
dc.identifier.doi10.1149/1.3206609en_US
dc.identifier.issn1938-5862en_US
dc.identifier.journalPHYSICS AND TECHNOLOGY OF HIGH-K GATE DIELECTRICS 7en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.3206609en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/150634
dc.identifier.wosnumberWOS:000338086300008en_US
dc.language.isoen_USen_US
dc.titleInAs-Channel Metal-Oxide-Semiconductor HEMTs with Atomic-Layer-Deposited Al2O3 Gate Dielectricen_US
dc.typeProceedings Paperen_US

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