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Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors

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dc.citation.epage1237en_US
dc.citation.spage1233en_US
dc.contributor.authorChen, Chih-Yangen_US
dc.contributor.authorWang, Tong-Yien_US
dc.contributor.authorMa, Ming-Wenen_US
dc.contributor.authorChen, Wei-Chengen_US
dc.contributor.authorLin, Hsiao-Yien_US
dc.contributor.authorYeh, Kuan-Linen_US
dc.contributor.authorWang, Shen-Deen_US
dc.contributor.authorLei, Tan-Fuen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:11:26Z
dc.date.available2014-12-08T15:11:26Z
dc.date.issued2007en_US
dc.description.abstractDynamic negative bias temperature instability in p-channel low-temperature poly-Si thin-film transistors was studied in this paper. The degradation of the devices was found to be voltage and temperature dependent. In addition, the frequency and duty ratio of the gate pulse affects the degree of the device degradation. The mechanism of the device degradation was investigated, and a physical model is proposed to explain the mechanism.en_US
dc.identifier.isbn978-7-5617-5228-9en_US
dc.identifier.journalAD'07: Proceedings of Asia Display 2007, Vols 1 and 2en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/8778
dc.identifier.wosnumberWOS:000248022601029
dc.language.isoen_USen_US
dc.subjectdynamic negative bias temperature instabilityen_US
dc.subjectthin-film transistoren_US
dc.titleDynamic negative bias temperature instability in low-temperature poly-Si thin-film transistorsen_US
dc.typeProceedings Paperen_US

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