A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

dc.citation.epage	61	en_US
dc.citation.spage	58	en_US
dc.contributor.author	Chen, GX	en_US
dc.contributor.author	Lee, CL	en_US
dc.contributor.author	Chen, JE	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:25:45Z
dc.date.available	2014-12-08T15:25:45Z
dc.date.issued	2004	en_US
dc.description.abstract	In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.	en_US
dc.identifier.isbn	0-7695-2235-1	en_US
dc.identifier.issn	1081-7735	en_US
dc.identifier.journal	13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18181
dc.identifier.wosnumber	WOS:000225878400010
dc.language.iso	en_US	en_US
dc.title	A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC	en_US
dc.type	Proceedings Paper	en_US

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