Transient-induced latchup in CMOS technology: Physical mechanism and device simulation

dc.citation.epage	940	en_US
dc.citation.spage	937	en_US
dc.contributor.author	Ker, MD	en_US
dc.contributor.author	Hsu, SF	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:25:43Z
dc.date.available	2014-12-08T15:25:43Z
dc.date.issued	2004	en_US
dc.description.abstract	The physical mechanism of (t) under bar ransient-induced (l) under bar atch (u) under barp (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level (e) under bar lectro (s) under bar tatic (d) under bar ischarge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.	en_US
dc.identifier.isbn	0-7803-8684-1	en_US
dc.identifier.journal	IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18127
dc.identifier.wosnumber	WOS:000227158500216
dc.language.iso	en_US	en_US
dc.title	Transient-induced latchup in CMOS technology: Physical mechanism and device simulation	en_US
dc.type	Proceedings Paper	en_US

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