Speeding Up Power Verification by Merging Equivalent Power Domains in RTL Design with UPF

Abstract

Low-power becomes a critical issue for modern VLSI designs. Unified Power Format (UPF) was invented for power management and enables the low-power design flow. In the UPF specification, controlling cells (including isolation cells, level shifter and retention cells) need to be placed properly to prevent unpredictable errors. Therefore, many commercial EDA tools support to examine the correctness of inserted cells and search missing/uncovered ones. However, such overall verification takes a long time for complex designs due to numerous power domains. Considering many of these power domains are equivalent and can be further merged, three strategies are proposed to explore (1) intra-scope domain equivalence, (2) inter-scope domain equivalence and (3) behavior-driven domain equivalence for RTL designs with UPF. For a case study on the OpenFire processor, the number of power domains is reduced from 4000+ to 500+, thus saving 77% time on signal checking in power verification.