On designing of 4-valued memory with double-gate TFT
| dc.citation.epage | 192 | en_US |
| dc.citation.spage | 187 | en_US |
| dc.contributor.author | Lee, CL | en_US |
| dc.contributor.author | Chern, HN | en_US |
| dc.contributor.author | Liao, MS | en_US |
| dc.contributor.author | Wang, HM | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:27:45Z | |
| dc.date.available | 2014-12-08T15:27:45Z | |
| dc.date.issued | 1995 | en_US |
| dc.identifier.isbn | 0-7803-2764-0 | en_US |
| dc.identifier.issn | 0195-623X | en_US |
| dc.identifier.journal | 1995 25TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/20013 | |
| dc.identifier.wosnumber | WOS:A1995BE33A00029 | |
| dc.language.iso | en_US | en_US |
| dc.subject | multi-valued logic | en_US |
| dc.subject | double-gate thin film transistor | en_US |
| dc.subject | SRAM | en_US |
| dc.subject | circuit design | en_US |
| dc.title | On designing of 4-valued memory with double-gate TFT | en_US |
| dc.type | Proceedings Paper | en_US |
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