Power Improvement for 65nm nMOSFET with High-Tensile CESL and Fast Nonlinear Behavior Modeling

Abstract

In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor was designed to work far from 50 ohms. By mean of this model, the accurate nonlinear behaviors of nMOSFET were obtained rapidly.