The performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gate
| dc.citation.epage | 39 | en_US |
| dc.citation.spage | 36 | en_US |
| dc.contributor.author | Tsai, HW | en_US |
| dc.contributor.author | Chiang, PY | en_US |
| dc.contributor.author | Chung, SS | en_US |
| dc.contributor.author | Kuo, DS | en_US |
| dc.contributor.author | Liang, MS | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:26:10Z | |
| dc.date.available | 2014-12-08T15:26:10Z | |
| dc.date.issued | 2003 | en_US |
| dc.description.abstract | In this paper, we proposed a simple approach for designing reliable and high performance p-channel Flash EEPROM cell from the floating-gate engineering point of view. In other words, a p-type doped floating gate used in a p-channel flash cell can achieve this goal. Results show that the programming speed, gate/drain disturb, read lifetime, and data retention in p-type floating-gate cell are much better than those of n-type floating-gate cell; except that p-type floating-gate cell has slower erasing speed. These results can be used as a guideline for designers to choose. | en_US |
| dc.identifier.doi | 10.1109/VTSA.2003.1252545 | en_US |
| dc.identifier.isbn | 0-7803-7765-6 | en_US |
| dc.identifier.journal | 2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/VTSA.2003.1252545 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/18558 | |
| dc.identifier.wosnumber | WOS:000189391000010 | |
| dc.language.iso | en_US | en_US |
| dc.title | The performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gate | en_US |
| dc.type | Proceedings Paper | en_US |