Optimization of the anti-punch-through implant for electrostatic discharge protection circuit design

Abstract

In this study, an optimal anti-punch-through implant for electrostatic discharge (ESD) protection devices is investigated. By solving a two-dimensional (2D) hydrodynamic (HD) device model as well as a lattice temperature equation numerically, the current density, carrier temperature, and parasitic capacitance of four different device structures are analyzed and compared for suppressing short-channel effects, reducing device heating, and improving ESD robustness simultaneously. The structure difference among these four devices is the location of anti-punch-through implantation; that is: (a) the Type 1 device is the control device without anti-punch-through implantation; (b) the Type 2 device is the device with anti-punch-through implantation under the source/drain extension; (c) the Type 3 device, with anti-punch-through implantation under the deep source/drain junction; and (d) the Type 4 device, with anti-punch-through implantation surrounding all junctions. By comparing these four device structures, we find that the Type 4 device not only has a lower electron temperature (and hence good thermal immunity) but also has a larger current density under an applied high bias. Therefore, this device maintains a higher driving capacity without producing a higher amount of heat and is suitable for the ESD protection device application.