Layout dependence on threshold voltage instability of hydrogenated amorphous silicon thin film transistors

Abstract

In this paper, we discuss the threshold voltage instability of two distinct layouts of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs). By simultaneously applying gate and drain bias stress, we show that the average threshold voltage shift of circular a-Si:H TFTs is 54% less than that of conventional inverted staggered a-Si:H TFTs. This result is primarily due to that the circular layout reduces the channel electron concentration. ISE-DESSIS (Integrated System Engineering DEvice Simulation for Smart Integrated Systems) was used to simulate the parallel electric field and obtain the total channel electron concentration. The simulation results closely correspond to the explanation in this study. These results indicate a significant impact of improving threshold voltage stability by a layout method.