A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit

dc.citation.epage	2026	en_US
dc.citation.spage	2023	en_US
dc.contributor.author	Wang, Chun-Kai	en_US
dc.contributor.author	Chen, Che-Sheng	en_US
dc.contributor.author	Wen, Kuei-Ann	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:21:20Z
dc.date.available	2014-12-08T15:21:20Z
dc.date.issued	2011	en_US
dc.description.abstract	A monolithic CMOS MEMS capacitive accelerometer with micropower analog readout circuit is presented in this paper. In order to optimize noise-power performance of accelerometer in limited area, a specification driven MEMS/IC co-design flow is adopted. In analog readout circuit design, the proposed circuit architecture combines chopper stabilization and correlated double sampling to suppress low frequency noise and compensate DC offset. The RMS input referred noise voltage is 9.82 nV/root Hz under 100Hz. The power consumption is 36uW at 100kHz modulation frequency.	en_US
dc.identifier.isbn	978-1-4244-9474-3	en_US
dc.identifier.issn	0271-4302	en_US
dc.identifier.journal	2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/15164
dc.identifier.wosnumber	WOS:000297265302088
dc.language.iso	en_US	en_US
dc.title	A Monolithic CMOS MEMS Accelerometer with Chopper Correlated Double Sampling Readout Circuit	en_US
dc.type	Proceedings Paper	en_US

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