Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection

dc.citation.epage	388	en_US
dc.citation.spage	385	en_US
dc.contributor.author	Chen, Wen-Yi	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Jou, Yeh-Ning	en_US
dc.contributor.author	Huang, Yeh-Jen	en_US
dc.contributor.author	Lin, Geeng-Lih	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:23:36Z
dc.date.available	2014-12-08T15:23:36Z
dc.date.issued	2009	en_US
dc.description.abstract	With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mu m 16-V BCD process. The TIP measured results confirmed that the secondary breakdown current (I(t2)) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.	en_US
dc.identifier.isbn	978-1-4244-3827-3	en_US
dc.identifier.journal	ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/16511
dc.identifier.wosnumber	WOS:000275929800097
dc.language.iso	en_US	en_US
dc.title	Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection	en_US
dc.type	Proceedings Paper	en_US

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