Study on ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Applications

dc.citation.epage		en_US
dc.citation.issue		en_US
dc.citation.volume		en_US
dc.contributor.author	Dai, Chia-Tsen	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:36:53Z
dc.date.available	2014-12-08T15:36:53Z
dc.date.issued	2014-01-01	en_US
dc.description.abstract	ESD protection with stacked low-voltage (LV) devices are proposed to form an area-efficient design for high-voltage (HV) applications in a 0.25-mu m HV BCD process. By using the stacked configuration, the LV devices can provide scalable triggering voltage (V-t1) and holding voltage (V-h) for various HV applications. Experimental results in silicon chip have verified that the stacked LV devices can exhibit a higher ESD robustness per unit layout area as comparing to the ESD clamp circuit with HV device.	en_US
dc.identifier.isbn	978-1-4799-3317-4	en_US
dc.identifier.issn	1541-7026	en_US
dc.identifier.journal	2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/25275
dc.identifier.wosnumber	WOS:000343833200138
dc.language.iso	en_US	en_US
dc.title	Study on ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Applications	en_US
dc.type	Proceedings Paper	en_US

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