A Multi-Bin Constant Throughput CABAC Decoder for HEVC

dc.citation.woscount	0	en_US
dc.contributor.author	Chen, Hsuan-Ku	en_US
dc.contributor.author	Fang, Chih-Chung	en_US
dc.contributor.author	Chang, Tian Sheuan	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2017-04-21T06:49:18Z
dc.date.available	2017-04-21T06:49:18Z
dc.date.issued	2015	en_US
dc.description.abstract	This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate count (810Mbins/sec) when operating at 270MHz.	en_US
dc.identifier.isbn	978-1-4799-7431-3	en_US
dc.identifier.journal	2015 IEEE JORDAN CONFERENCE ON APPLIED ELECTRICAL ENGINEERING AND COMPUTING TECHNOLOGIES (AEECT)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/135961
dc.identifier.wosnumber	WOS:000380878900018	en_US
dc.language.iso	en_US	en_US
dc.subject	HEVC	en_US
dc.subject	CABAC	en_US
dc.subject	Decoder	en_US
dc.subject	VLSI	en_US
dc.title	A Multi-Bin Constant Throughput CABAC Decoder for HEVC	en_US
dc.type	Proceedings Paper	en_US

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