Pin-out designation method for package-board codesign
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 08302067 | zh_TW |
| dc.contributor.author | Lee Ren-Jie | en_US |
| dc.contributor.author | Chen Hung-Ming | en_US |
| dc.date.accessioned | 2014-12-16T06:14:09Z | |
| dc.date.available | 2014-12-16T06:14:09Z | |
| dc.date.issued | 2012-10-30 | en_US |
| dc.description.abstract | A pin out designation method for package board codesign has steps of defining pin characteristics and requirements, generating multiple pin patterns, pin blocks construction and grouping and pin blocks floorplanning. Designers may use an EDA tool to generate multiple pin patterns and may use the pin patterns to construct multiple pin blocks, to group the pin blocks around four sides of a chip and to adjust the pin blocks into a minimized package size of the chip. | zh_TW |
| dc.identifier.govdoc | G06F017/50 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/104534 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | Pin-out designation method for package-board codesign | zh_TW |
| dc.type | Patents | en_US |