A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
| dc.citation.epage | 140 | en_US |
| dc.citation.spage | 137 | en_US |
| dc.contributor.author | Chung, Yung-Hui | en_US |
| dc.contributor.author | Wu, Jieh-Tsorng | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.date.accessioned | 2014-12-08T15:21:05Z | |
| dc.date.available | 2014-12-08T15:21:05Z | |
| dc.date.issued | 2009 | en_US |
| dc.description.abstract | a 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power dissipation, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The linearity of the residue amplifier is enhanced by digital background calibration. The resolution of the comparators is improved by analog offset calibration. The ADC consumes 6mW from a 1V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34b. The FOM is 100 fJ per conversion-step. | en_US |
| dc.identifier.doi | 10.1109/ASSCC.2009.5357197 | en_US |
| dc.identifier.isbn | 978-1-4244-4434-2 | en_US |
| dc.identifier.journal | 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ASSCC.2009.5357197 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/14996 | |
| dc.identifier.wosnumber | WOS:000298194200035 | |
| dc.language.iso | en_US | en_US |
| dc.title | A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC | en_US |
| dc.type | Proceedings Paper | en_US |