High Resolution Comparator Design For RF Imager

dc.citation.epage	69	en_US
dc.citation.spage	65	en_US
dc.citation.woscount	0	en_US
dc.contributor.author	Pandey, Rajeev Kumar	en_US
dc.contributor.author	Pandey, Sanjeev Kumar	en_US
dc.contributor.department	電機資訊國際碩士學位學程	zh_TW
dc.contributor.department	EECS International Graduate Program-Master	en_US
dc.date.accessioned	2019-05-02T00:26:46Z
dc.date.available	2019-05-02T00:26:46Z
dc.date.issued	2018-01-01	en_US
dc.description.abstract	This paper proposes a design of high resolution regenerative latch based comparator for Multi Ramp Multi slope ADC of RF 3D imager. The minimum sense voltage for the design comparator is 500nV. A wide swing-self biased fully differential folded cascode amplifier used as analog front end for regenerative latch. Due to fully differential architecture of the comparator noise immunity is high. Simulation is done by using TSMC 0.18um with 1.8V supply. The total Power consumption of design comparator is 0.842mW and total delay is 11 mu s.	en_US
dc.identifier.isbn	978-1-5386-7336-2	en_US
dc.identifier.journal	2018 IEEE RECENT ADVANCES IN INTELLIGENT COMPUTATIONAL SYSTEMS (RAICS)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/151708
dc.identifier.wosnumber	WOS:000462370200014	en_US
dc.language.iso	en_US	en_US
dc.subject	RF imager	en_US
dc.subject	Cascode Amplifier	en_US
dc.subject	SR Latch	en_US
dc.subject	Regenerative Latch	en_US
dc.subject	Comparator	en_US
dc.title	High Resolution Comparator Design For RF Imager	en_US
dc.type	Proceedings Paper	en_US

Files

Now showing 1 - 1 of 1