Structure and process of basic complementary logic gate made by junctionless transistors
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20120126197 | zh_TW |
| dc.contributor.author | Chung Steve S. | en_US |
| dc.contributor.author | Hsieh E. R. | en_US |
| dc.date.accessioned | 2014-12-16T06:15:13Z | |
| dc.date.available | 2014-12-16T06:15:13Z | |
| dc.date.issued | 2012-05-24 | en_US |
| dc.description.abstract | The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc. | zh_TW |
| dc.identifier.govdoc | H01L027/092 | zh_TW |
| dc.identifier.govdoc | H01L021/782 | zh_TW |
| dc.identifier.govdoc | H01L021/8238 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/105177 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | Structure and process of basic complementary logic gate made by junctionless transistors | zh_TW |
| dc.type | Patents | en_US |