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A 242mW, 10mm(2) 1080p H.264/AVC high profile encoder chip

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dc.citation.epage83en_US
dc.citation.spage78en_US
dc.contributor.authorLin, Yu-Kunen_US
dc.contributor.authorLi, De-Weien_US
dc.contributor.authorLin, Chia-Chunen_US
dc.contributor.authorKuo, Tzu-Yunen_US
dc.contributor.authorWu, Sian-Jinen_US
dc.contributor.authorTai, Wei-Chengen_US
dc.contributor.authorChang, Wei-Chengen_US
dc.contributor.authorChang, Tian-Sheuanen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:03:18Z
dc.date.available2014-12-08T15:03:18Z
dc.date.issued2008en_US
dc.description.abstractA 1080p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mu m CMOS technology with an area of 10 mm(2) and 242mW at 145MHz. Compared to the state-of-the-art design targeted at 720p baseline, this design reduces 53.4% power and 46.7% area through parallelism enhanced throughput and cross stage sharing pipeline.en_US
dc.identifier.isbn978-1-60558-115-6en_US
dc.identifier.issn0738-100Xen_US
dc.identifier.journal2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/1852
dc.identifier.wosnumberWOS:000258930200017
dc.language.isoen_USen_US
dc.subjectH.264en_US
dc.subjectencoderen_US
dc.subjecthigh profileen_US
dc.subject1080pen_US
dc.titleA 242mW, 10mm(2) 1080p H.264/AVC high profile encoder chipen_US
dc.typeProceedings Paperen_US

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