Design and implementation of a scalable fast Fourier transform core

dc.citation.epage	298	en_US
dc.citation.spage	295	en_US
dc.contributor.author	Sung, CH	en_US
dc.contributor.author	Lee, KB	en_US
dc.contributor.author	Jen, CW	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:26:36Z
dc.date.available	2014-12-08T15:26:36Z
dc.date.issued	2002	en_US
dc.description.abstract	A novel approach for scalable length Fast Fourier Transform (FFT) in single Processing Element (single PE) architecture has been developed. Scalable length FFT design meets the different lengths requirement of FFT operation in OFDM system [1]. An efficient mechanism that named Interleaved Rotated Data Allocation (IRDA) to replace multiple-port memory with single-port memory has also been proposed. Using single-port memory instead of multiple-port memory makes more area efficient.	en_US
dc.identifier.isbn	0-7803-7363-4	en_US
dc.identifier.journal	2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18903
dc.identifier.wosnumber	WOS:000180272700074
dc.language.iso	en_US	en_US
dc.title	Design and implementation of a scalable fast Fourier transform core	en_US
dc.type	Proceedings Paper	en_US

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