Design-for-digital-testability 30 MHz second-order Sigma-Delta modulator

dc.citation.epage	214	en_US
dc.citation.spage	211	en_US
dc.contributor.author	Hong, HC	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.date.accessioned	2014-12-08T15:25:53Z
dc.date.available	2014-12-08T15:25:53Z
dc.date.issued	2004	en_US
dc.description.abstract	A purely digitally testable second-order Sigma-Delta modulator is presented. In the test mode, the input stage of the modulator is reconfigured to accept a repetitive Sigma-Delta modulated bit-stream as its stimulus. The proposed test scheme has a low cost, a high fault coverage, high measurement accuracy, and is able to do the at-speed tests. The experimental results show that the dynamic range measured with the digital stimulus is only 2 dB inferior to that with its analog counterpart.	en_US
dc.identifier.isbn	0-7803-8495-4	en_US
dc.identifier.journal	PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18317
dc.identifier.wosnumber	WOS:000224961000044
dc.language.iso	en_US	en_US
dc.title	Design-for-digital-testability 30 MHz second-order Sigma-Delta modulator	en_US
dc.type	Proceedings Paper	en_US

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