On the study of logarithmic time parallel adders
| dc.citation.epage | 466 | en_US |
| dc.citation.spage | 459 | en_US |
| dc.contributor.author | Yeh, WC | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:27:03Z | |
| dc.date.available | 2014-12-08T15:27:03Z | |
| dc.date.issued | 2000 | en_US |
| dc.description.abstract | This work formulates a set of equations to describe logarithmic time parallel adders. The equations can be used to explain several popular fast adder schemes and derive new adder schemes easily. It is shown that if there is an adder constructed from conditional-sum rule, then we can always obtain another adder based on carry-lookahead rule with equivalent topology and structure, and vice versa. | en_US |
| dc.identifier.isbn | 0-7803-6488-0 | en_US |
| dc.identifier.journal | 2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/19273 | |
| dc.identifier.wosnumber | WOS:000165893400046 | |
| dc.language.iso | en_US | en_US |
| dc.title | On the study of logarithmic time parallel adders | en_US |
| dc.type | Proceedings Paper | en_US |
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