Process-related reliability issues toward sub-100 nm device regime
| dc.citation.epage | 140 | en_US |
| dc.citation.spage | 133 | en_US |
| dc.contributor.author | Chang, CY | en_US |
| dc.contributor.author | Chao, TS | en_US |
| dc.contributor.author | Lin, HC | en_US |
| dc.contributor.author | Chien, CH | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.date.accessioned | 2014-12-08T15:26:29Z | |
| dc.date.available | 2014-12-08T15:26:29Z | |
| dc.date.issued | 2002 | en_US |
| dc.description.abstract | Crucial process-related reliability issues, such as boron penetration, plasma charging damage, metal-gate processing, and emerging high-k dielectric, toward sub-100 nm technology nodes have been discussed. | en_US |
| dc.identifier.isbn | 0-7803-7235-2 | en_US |
| dc.identifier.issn | 2159-1660 | en_US |
| dc.identifier.journal | 2002 23RD INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/18811 | |
| dc.identifier.wosnumber | WOS:000176359700019 | |
| dc.language.iso | en_US | en_US |
| dc.title | Process-related reliability issues toward sub-100 nm device regime | en_US |
| dc.type | Proceedings Paper | en_US |
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