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TAG MEMORY AND CACHE SYSTEM WITH AUTOMATING TAG COMPARISON MECHANISM AND CACHE METHOD THEREOF

dc.citation.patentcountryUSAen_US
dc.citation.patentnumber20170220480en_US
dc.contributor.authorTien-Fu Chenen_US
dc.contributor.authorMeng-Fan Changen_US
dc.contributor.authorKeng-Hao Yangen_US
dc.date.accessioned2019-04-11T05:47:34Z
dc.date.available2019-04-11T05:47:34Z
dc.date.issued2017-08-03en_US
dc.description.abstractA tag memory and a cache system with automating tag comparison mechanism and a cache method thereof are provided. The tag memory in the cache system includes a memory cell array, sensing amplifiers and a tag comparison circuit. The memory cell array stores cache tags, and outputs row tags of the cache tags according to an index in a memory address. The sensing amplifiers perform signal amplifications on the row tags to serve as comparison tags. The tag comparison circuit performs parallel comparisons between a target tag in the memory address and the row tags. When one of the row tags matches the target tag, the tag comparison circuit outputs a location of the matched row tag to serve as a first column address. The first column address is a column address where the memory address corresponds to a first data memory in the cache system.en_US
dc.identifier.govdocG06F012/08en_US
dc.identifier.govdocG06F012/10en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/151294
dc.language.isoen_USen_US
dc.titleTAG MEMORY AND CACHE SYSTEM WITH AUTOMATING TAG COMPARISON MECHANISM AND CACHE METHOD THEREOFen_US
dc.typePatentsen_US

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