Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
| dc.citation.epage | 595 | en_US |
| dc.citation.spage | 594 | en_US |
| dc.contributor.author | Ker, Ming-Dou | en_US |
| dc.contributor.author | Wang, Chang-Tzu | en_US |
| dc.contributor.author | Tang, Tien-Hao | en_US |
| dc.contributor.author | Su, Kuan-Cbeng | en_US |
| dc.contributor.department | 電機學院 | zh_TW |
| dc.contributor.department | College of Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:15:11Z | |
| dc.date.available | 2014-12-08T15:15:11Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1xVDD devices for 3xVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mu m CMOS process with only 1.2-V devices. | en_US |
| dc.identifier.doi | 10.1109/RELPHY.2007.369967 | en_US |
| dc.identifier.isbn | 978-1-4244-0918-1 | en_US |
| dc.identifier.journal | 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/RELPHY.2007.369967 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/11412 | |
| dc.identifier.wosnumber | WOS:000246989600108 | |
| dc.language.iso | en_US | en_US |
| dc.title | Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes | en_US |
| dc.type | Proceedings Paper | en_US |