用於軟體無線電基頻處理之系統晶片設計技術---子計畫III：數位訊號處理器與可重置加速器之設計(II)

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dc.contributor.author任建葳en_US
dc.contributor.department國立交通大學電子工程學系zh_TW
dc.date.accessioned2014-12-13T10:33:30Z
dc.date.available2014-12-13T10:33:30Z
dc.date.issued2003en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.identifier.govdocNSC92-2220-E009-020zh_TW
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=844309&docId=160006en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/92102
dc.language.isozh_TWen_US
dc.title用於軟體無線電基頻處理之系統晶片設計技術---子計畫III：數位訊號處理器與可重置加速器之設計(II)zh_TW
dc.titleThe Design of DSP Processor Core and Configurable Accelerator (II)en_US
dc.typePlanen_US

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