Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions
| dc.citation.epage | 336 | en_US |
| dc.citation.spage | 333 | en_US |
| dc.contributor.author | Cheng, C. F. | en_US |
| dc.contributor.author | Wu, C. H. | en_US |
| dc.contributor.author | Su, N. C. | en_US |
| dc.contributor.author | Wang, S. J. | en_US |
| dc.contributor.author | McAlister, S. P. | en_US |
| dc.contributor.author | Chin, Albert | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:09:24Z | |
| dc.date.available | 2014-12-08T15:09:24Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS. | en_US |
| dc.identifier.doi | 10.1109/IEDM.2007.4418939 | en_US |
| dc.identifier.isbn | 978-1-4244-1507-6 | en_US |
| dc.identifier.journal | 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/IEDM.2007.4418939 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/7168 | |
| dc.identifier.wosnumber | WOS:000259347800074 | |
| dc.language.iso | en_US | en_US |
| dc.title | Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions | en_US |
| dc.type | Article | en_US |