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METHOD FOR PARAMETER EXTRACTION OF A SEMICONDUCTOR DEVICE

dc.citation.patentcountryUSAen_US
dc.citation.patentnumber20170242065en_US
dc.contributor.authorJyh-Chyurn GUOen_US
dc.contributor.authorYen-Ying LINen_US
dc.date.accessioned2019-04-11T05:47:35Z
dc.date.available2019-04-11T05:47:35Z
dc.date.issued2017-08-24en_US
dc.description.abstractA method is provided for parameter extraction of a semiconductor device with a multi-finger gate. The method includes measuring gate-to-source and gate-to-drain capacitances and performing 3D simulation to compute fringing capacitances, thereby computing an overlap capacitance between the gate and a source/drain extension region, and computing a length of the source/drain extension region according to the overlap capacitance.en_US
dc.identifier.govdocG01R031/26en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/151297
dc.language.isoen_USen_US
dc.titleMETHOD FOR PARAMETER EXTRACTION OF A SEMICONDUCTOR DEVICEen_US
dc.typePatentsen_US

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