An on-chip jitter measurement circuit for the PLL

dc.citation.epage	335	en_US
dc.citation.spage	332	en_US
dc.contributor.author	Tsai, CC	en_US
dc.contributor.author	Lee, CL	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:26:01Z
dc.date.available	2014-12-08T15:26:01Z
dc.date.issued	2003	en_US
dc.description.abstract	A simple built-on-chip PLL jitter measurement circuit, which utilizes the vernier delay line principle, transforms timing difference signals into digital words and has a self calibration capability to minimize the mismatched error caused by the process variation, is proposed and demonstrated.	en_US
dc.identifier.isbn	0-7695-1951-2	en_US
dc.identifier.journal	ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18434
dc.identifier.wosnumber	WOS:000189157300060
dc.language.iso	en_US	en_US
dc.title	An on-chip jitter measurement circuit for the PLL	en_US
dc.type	Proceedings Paper	en_US

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