STATIC MEMORY CELL
| dc.citation.patentcountry | USA | zh_TW |
| dc.citation.patentnumber | 20150162077 | zh_TW |
| dc.contributor.author | Chuang Ching-Te | en_US |
| dc.contributor.author | Chang Chih-Hao | en_US |
| dc.contributor.author | Chung Chao-Kuei | en_US |
| dc.contributor.author | Lu Chien-Yu | en_US |
| dc.contributor.author | Jou Shyh-Jye | en_US |
| dc.contributor.author | Tu Ming-Hsien | en_US |
| dc.date.accessioned | 2015-12-04T07:03:10Z | |
| dc.date.available | 2015-12-04T07:03:10Z | |
| dc.date.issued | 2015-06-11 | en_US |
| dc.description.abstract | A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data. | zh_TW |
| dc.identifier.govdoc | G11C011/412 | zh_TW |
| dc.identifier.govdoc | G11C011/419 | zh_TW |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/128670 | |
| dc.language.iso | zh_TW | en_US |
| dc.title | STATIC MEMORY CELL | zh_TW |
| dc.type | Patents | en_US |