ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration
| dc.citation.epage | 90 | en_US |
| dc.citation.spage | 85 | en_US |
| dc.contributor.author | Ker, MD | en_US |
| dc.contributor.author | Chuang, CH | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:26:45Z | |
| dc.date.available | 2014-12-08T15:26:45Z | |
| dc.date.issued | 2001 | en_US |
| dc.identifier.isbn | 0-7803-6675-1 | en_US |
| dc.identifier.journal | PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/19014 | |
| dc.identifier.wosnumber | WOS:000171369600012 | |
| dc.language.iso | en_US | en_US |
| dc.title | ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration | en_US |
| dc.type | Proceedings Paper | en_US |
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