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A High-Performance Multibit-Flipping Algorithm for LDPC Decoding

dc.citation.epage283en_US
dc.citation.spage280en_US
dc.contributor.authorHung, Jui-Huien_US
dc.contributor.authorChen, Sau-Geeen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2014-12-08T15:17:50Z
dc.date.available2014-12-08T15:17:50Z
dc.date.issued2009en_US
dc.description.abstractFor LDPC decoding, bit-flipping (BF) algorithms are much simpler than the min-sum algorithms (MSA). However, BF algorithms have the disadvantages of poorer performances and higher iteration counts than MSA. This paper introduces the concepts of low correlation search and culprit vote to further improve the efficiency of the existing BF algorithms. High decoding performances and low iteration number are achieved by flipping those bits with low correlation as much as possible and introducing an additional syndrome vote procedure. As a result, the proposed algorithm can achieve significant decoding performance which is very close to the min-sum algorithm (MSA) but with much lower computation complexity.en_US
dc.identifier.isbn978-981-08-2468-6en_US
dc.identifier.journalPROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009)en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/12923
dc.identifier.wosnumberWOS:000290361900070
dc.language.isoen_USen_US
dc.subjectchannel codingen_US
dc.subjectLDPC codesen_US
dc.subjectbit-flipping algorithmen_US
dc.titleA High-Performance Multibit-Flipping Algorithm for LDPC Decodingen_US
dc.typeProceedings Paperen_US

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